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DS1245Y/AB 1024k Nonvolatile SRAM
www.dalsemi.com
FEATURES
10 years minimum data retention in the absence of external power Data is automatically protected during power loss Replaces 128k x 8 volatile static RAM, EEPROM or Flash memory Unlimited write cycles Low-power CMOS Read and write access times as fast as 70 ns Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Full 10% VCC operating range (DS1245Y) Optional 5% VCC operating range (DS1245AB) Optional industrial temperature range of -40C to +85C, designated IND JEDEC standard 32-pin DIP package New PowerCap Module (PCM) package - Directly surface-mountable module - Replaceable snap-on PowerCap provides lithium backup battery - Standardized pinout for all nonvolatile SRAM products - Detachment feature on PowerCap allows easy removal using a regular screwdriver
PIN ASSIGNMENT
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 NC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
32-PIN ENCAPSULATED PACKAGE 740 MIL EXTENDED
NC NC A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
NC A15 A16 NC VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
GND VBAT
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
34-PIN POWERCAP MODULE (PCM) (USES DS9034PC POWERCAP)
PIN DESCRIPTION
A0 - A16 DQ0 - DQ7
CE WE OE
VCC GND NC 1 of 12
- Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Power (+5V) - Ground - No Connect 111899
DS1245Y/AB
DESCRIPTION
The DS1245 1024k Nonvolatile SRAMs are1,048,576-bit, fully static, nonvolatile SRAMs organized as 131,072 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package DS1245 devices can be used in place of existing 128k x 8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1245 devices in the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1245 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 17 address inputs (A0 A16) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1245 executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1245AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1245Y provides full functional capability for VCC greater than 4.5 volts and writeprotects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write-protect themselves, all inputs become "don't care," and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1245AB and 4.5 volts for the DS1245Y.
FRESHNESS SEAL
Each DS1245 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than 4.25 volts, the lithium energy source is enabled for battery back-up operation.
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DS1245Y/AB
PACKAGES
The DS1245 devices are available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1245 PCM device to be surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow soldering. After a DS1245 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper attachment. DS1245 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * -0.3V to +7.0V 0C to 70C, -40C to +85C for Ind parts -40C to +70C, -40C to +85C for Ind parts 260C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER DS1245AB Power Supply Voltage DS1245Y Power Supply Voltage Logic 1 Logic 0 SYMBOL VCC VCC VIH VIL MIN 4.75 4.5 2.2 0.0 TYP 5.0 5.0 MAX 5.25 5.5 VCC 0.8
(tA: See Note 10)
UNITS V V V V NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current I/O Leakage Current CE VIH VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CE =2.2V Standby Current CE =VCC-0.5V Operating Current Write Protection Voltage (DS1245AB) Write Protection Voltage (DS1245Y)
(VCC=5V =5% for DS1245AB) (tA: See Note 10) (VCC=5V =10% for DS1245Y)
SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICCO1 VTP VTP 4.50 4.25 4.62 4.37 MIN -1.0 -1.0 -1.0 2.0 5.0 3.0 10.0 5.0 85 4.75 4.5 TYP MAX +1.0 +1.0 UNITS A A mA mA mA mA mA V V NOTES
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DS1245Y/AB
CAPACITANCE
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP 5 5 MAX 10 10
(tA=25C)
UNITS pF pF NOTES
AC ELECTRICAL CHARACTERISTICS
(VCC=5V =5% for DS1245AB) (tA: See Note 10) (VCC=5V =10% for DS1245Y)
DS1245AB-70 DS1245Y-70 DS1245AB-85 DS1245Y-85
PARAMETER Read Cycle Time Access Time
OE CE OE
SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2
MIN 70
MAX 70 35 70
MIN 85
MAX 85 45 85
UNITS ns ns ns ns ns
NOTES
to Output Valid to Output Valid or CE to Output Active
5 25 5 70 55 0 5 15 25 5 30 0 10
5 30 5 85 65 0 5 15 30 5 35 0 10
5 5
Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time
ns ns ns ns ns ns ns ns ns ns ns ns
3 12 13 5 5 4 12 13
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DS1245Y/AB
AC ELECTRICAL CHARACTERISTICS
(VCC=5V =5% for DS1245AB) (tA: See Note 10) (VCC=5V =10% for DS1245Y)
DS1245AB-100 DS1245Y-100 DS1245AB-120 DS1245Y-120
PARAMETER Read Cycle Time Access Time
OE CE OE
SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2
MIN 100
MAX 100 50 100
MIN 120
MAX 120 60 120
UNITS ns ns ns ns ns
NOTES
to Output Valid to Output Valid or CE to Output Active
5 35 5 100 75 0 5 15 35 5 40 0 10
5 35 5 120 90 0 5 15 35 5 50 0 10
5 5
Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time
ns ns ns ns ns ns ns ns ns ns ns ns
3 12 13 5 5 4 12 13
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DS1245Y/AB
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
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DS1245Y/AB
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITION
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DS1245Y/AB
POWER-DOWN/POWER-UP TIMING
PARAMETER
CE , WE
(tA: See Note 10)
MIN 0 300 300 2 125 TYP MAX UNITS s s s ms NOTES 11
at VIH before Power-Down
SYMBOL tPD tF tR tREC
VCC slew from VTP to 0V ( CE at VIH) VCC slew from 0V to VTP ( CE at VIH)
CE , WE
at VIH after Power-Up
(tA=25C)
PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a Read Cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH, tDS are measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. Each DS1245 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0C to 70C. For industrial products (IND), this range is -40C to +85C. 11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 and tDH1 are measured from WE going high. 13. tWR2 and tDH2 are measured from CE going high. 14. DS1245 DIP modules are recognized by Underwriters Laboratory (U.L.) under file E99151. DS1245 PowerCap modules are pending U.L. review. Contact the factory for status.
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DS1245Y/AB
DC TEST CONDITIONS
Outputs Open Cycle = 200 ns for operating current All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 - 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
DS1245 TTP - SSS - III Operating Temperature Range blank: 0 to 70 IND: -40 to +85C Access Speed 70: 70 ns 85: 85 ns 100: 100 ns 120: 120 ns Package Type blank: 32-pin 600-mil DIP P: 34-pin PowerCap Module VCC Tolerance AB: 5% Y: 10%
DS1245Y/AB NONVOLATILE SRAM, 32-PIN, 740-MIL EXTENDED DIP MODULE
PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 32-PIN MIN 1.680 42.67 0.720 18.29 0.355 9.02 0.080 2.03 0.015 0.38 0.120 3.05 0.090 2.29 0.590 14.99 0.008 0.20 0.015 0.38 MAX 1.700 43.18 0.740 18.80 0.375 9.52 0.110 2.79 0.025 0.63 0.160 4.06 0.110 2.79 0.630 16.00 0.012 0.30 0.021 0.53
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DS1245Y/AB
DS1245Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE
PKG DIM A B C D E F G INCHES MIN 0.920 0.980 0.052 0.048 0.015 0.020 NOM 0.925 0.985 0.055 0.050 0.020 0.025 MAX 0.930 0.990 0.080 0.058 0.052 0.025 0.030
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DS1245Y/AB
DS1245Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE WITH POWERCAP
PKG DIM A B C D E F G INCHES MIN 0.920 0.955 0.240 0.052 0.048 0.015 0.020 NOM 0.925 0.960 0.245 0.055 0.050 0.020 0.025 MAX 0.930 0.965 0.250 0.058 0.052 0.025 0.030
ASSEMBLY AND USE
Reflow soldering Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented label-side up (live-bug). Hand soldering and touch-up Do not touch soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove part, apply flux, heat pad until solder reflows, and use a solder wick. LPM replacement in a socket To replace a Low Profile Module in a 68-pin PLCC socket, attach a DS9034PC PowerCap to a module base then insert the complete module into the socket one row of leads at a time, pushing only on the corners of the cap. Never apply force to the center of the device. To remove from a socket, use a PLCC extraction tool and ensure that it does not hit or damage any of the module IC components. Do not use any other tool for extraction. 11 of 12
DS1245Y/AB
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG DIM A B C D E INCHES MIN NOM 1.050 0.826 0.050 0.030 0.112 MAX -
RECOMMENDED POWERCAP MODULE SOLDER STENCIL
PKG DIM A B C D E INCHES MIN NOM 1.050 0.890 0.050 0.030 0.080 MAX -
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